The present invention relates to a capacitor digital-to-analog converter (CDAC) for use in integrated circuits. More particularly, the present invention relates to a CDAC configured to operate at low supply voltages, for example at supply voltages of 2.5 volts or less.
The demand for more reliable analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and related components for use in communication, data acquisition, and battery operated applications continues to increase. As a result, integrated circuit manufacturers are requiring for such converters and devices to continue to improve their operating performance to meet the design requirements of a myriad of emerging applications.
A block diagram of an exemplary ADC is illustrated in FIG. 1. The ADC includes an analog input, e.g., a differential input, for receiving an analog voltage signal. In addition, the ADC is configured for providing a digital output, for example, a 16 bit digital serial word. Such ADC devices are generally configured for operation at various supply voltages, for example, at a supply voltage of approximately 5 volts, with a external reference configured for half the supply voltage, or for 2.5 volts. The ADC also includes an output span or conversion ratio comprising plus or minus the external reference voltage. For example, for a differential input device, the positive +IN terminal and the negative xe2x88x92IN terminal of the ADC are configured such that the terminals cannot be more than 2.5 volts apart in magnitude, with the conversion ratio in either direction, i.e., if the negative xe2x88x92IN terminal is fixed at 2.5 volts, the positive +IN terminal can vary between zero and 5 volts, but cannot swing past the power supply.
In battery-operated systems, it is desirable for CDAC devices to be capable of operating with as low a supply voltage as possible so that as the supply voltage drops, the CDAC can continue to function as desired. For example, some CDAC applications utilize a stack of battery cells to maintain the supply voltage level. However, as the stored charge of the cells is depleted, the battery voltage will continue to drop until the CDAC or other component part is no longer operational. Typically, these CDAC parts are configured with a 5 volt supply and are designed to operate with as little as 2.7 volts being supplied by the battery. Configuring the CDAC components to operate effectively with as little as 10% less supply voltage, e.g., with a 2.4 volts battery supply, is extremely difficult to accomplish. Nevertheless, it is expected that future applications will demand for CDAC components to operate at significantly lower supply voltages, for example, with battery supplies under 2 volts.
One possible approach to get the CDAC components to operate at lower supply voltages could include the utilization of a lower threshold MOSFET process. However, these MOSFET-based processes having lower thresholds are expensive to develop and manufacture, i.e., these MOSFET solutions are generally cost prohibitive, as opposed to applications using more desirable, standard CMOS processes. Further, these MOSFET-based processes still do not yield components that can operate at the lower supply voltage levels expected to be demanded in the future.
In addition to operating at low supply voltages, the components need to be able to operate at normal operating speeds. While some prior art attempts have been developed that provide CDAC devices that can operate at voltage levels as low as 1.9 volts, these devices have also been designed to operate at very slow speeds, such that the devices are not usable for most applications. Instead, the CDAC components need to be configured to operate not only at lower supply voltages, but also at a higher performance levels, for example, at higher data rates and processing speeds.
There are a couple of reasons that CDAC devices have difficulty operating at low supply voltages. One reason is the common-mode input range of the comparator, which is limited by the P-channel input of the differential pair of the comparator. Any loss to the input stage of the comparator is constant regardless of the supply voltage, so the effect of the comparator is more profound with lower power supplies.
However, the most prevailing reason that currently available CDAC devices have problem operating a low supply voltages is the inherent problem with the sampling bit switches for the CDAC. For example, with reference to a bit switch configured for a 5 volt supply, as illustrated in FIG. 2, these sampling bit switches are typically developed through the building of a transmission gate comprising a P-channel device and an N-channel device. The transmission gate can be connected to a 5 volt supply, VSUPPLY, e.g., the P-channel device can have its gate electrode connected to zero volts and the N-channel device can have its gate electrode connected to a 5 volt supply. In addition, the respective drains of the P-channel and N-channel devices are connected together to a reference voltage, VREF, which is generally configured for half the 5 volt supply, or 2.5 volts. Finally, the respective sources of the P-channel and N-channel devices are connected to a sampling capacitor, CS. Accordingly, when the logic of the CDAC is turned on, the bit switch receives a 5 volt supply, and the transmission gate is configured to charge up the capacitor to the reference voltage of 2.5 volts, i.e., when turned on, the gate-source voltage, VGS, of the P-channel device is 2.5 volts and the gate-source voltage of the N-channel device is xe2x88x922.5 volts.
The transmission gates of the bit switches include a threshold voltage that must be exceeded before the P-channel or N-channel devices will effectively turn on, and thus charge the sampling capacitor CS. This threshold voltage over temperature typically varies between 1.1 and 1.2 volts. Accordingly, the 2.5 volts provided by the reference voltage VREF is usually adequate to turn on the devices. However, as the supply voltage decreases from a span of 0 to 5 volts to a span of 0 to 2 volts, the reference voltage VREF drops to approximately 1 volt, resulting in only 1 volt at the transmission gate. Such a low voltage is generally insufficient to overcome the threshold voltage and thus turn on the transmission gates, at least not in a manner to permit operation of the bit switch to suitably charge the capacitor, i.e., at lower supply voltages, the transmission gates develop high impedance bands or dead bands in their transfer functions which prevent effective operation. Further decreases of the supply voltage, for example, to 1.8 volts or less, render the transmission gates, and thus the CDAC, inoperable as the transmission gates are switched off.
Such a problem with the reference voltage or input voltage failing to exceed the threshold voltage at the transmission gates can occur at several instances in the CDAC. For example, in addition to occurring at the bit switches, the above problems also occur at the mid-point switches and any auto-zero switches in the comparator. In other words, on each occasion that a transmission gate is configured to operate at mid-range power supply, for example, at 2.5 volts or less, the transmission gate will be difficult to turn on, and thus the CDAC will be rendered inoperable. Moreover, these threshold problems are typically worse for full differential parts, such as CDAC devices having a +/xe2x88x92VREF reference voltage, than for single-ended components, such as CDAC devices having a 0 to VREF reference voltage. For example, these differential parts typically utilize a reference voltage comprising xc2xd the full-scale range while single-ended parts utilize a full-scale reference. This characteristic for differential parts manifests itself as differential linearity errors above mid-range operation after the most significant bit (MSB) is turned xe2x80x9con.xe2x80x9d Still further, in applications where the reference voltage is replaced with a varying input signal, when the input signal level approaches mid-range, e.g., 1.2 volts or less, there is not enough voltage to overcome the threshold levels and thus turn xe2x80x9conxe2x80x9d the transmission gates.
One solution considered for overcoming the threshold voltage of the transmission gate is the use of a charge pumping configuration to charge pump the power supply to a higher voltage. However, such a charge pumping configuration requires high power consumption, including the requirement of a significantly large charge pump comprising a very large capacitor device, thus rendering the solution impracticable for most applications.
Accordingly, a need exists for a CDAC that can be configured to operate at lower supply voltages, for example, less than 2.5 volts. In addition, a need exists for a CDAC that can operate at lower supply voltages while maintaining high performance levels, such as high speed and data rates.
The method and circuit according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a CDAC is provided that can operate at low supply voltages, for example, at supply voltages of 2.5 volts or less. In accordance with one aspect of the present invention, switches in the CDAC, such as sampling bit switches, are gate-boosted to permit the voltage at the transmission gates to exceed the threshold voltage and thus permit the transmission gates to effectively operate. As a result, the CDAC can continue to operate, even with the existence of lower power supply voltages. In accordance with an exemplary embodiment, a gate-boosting circuit comprises a pair of N-channel transistor devices and a charging capacitor configured to provide a gate-boosting voltage to the transmission gates.
In accordance with another aspect of the present invention, the gate boosting circuit can comprise conventional CMOS devices, rather than more expensive low threshold MOSFET devices. Moreover, the gate-boosting circuit can be configured with various switches in the CDAC circuit, such as bit sampling switches, mid-point switches, and auto-zero switches.